Chad Wallace @siliconcodesign
Deep-Tech Semiconductor Analyst, MSEE @JohnsHopkins. Expert-driven system architecture deep-dives of AI datacenter hardware at https://t.co/atebRcUn6C siliconcodesign.com Austin, TX Joined April 2025-
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Lots of discussion about FP formats with David Patterson (@FelixCLC_ name checked by @IanCutress )
Front and center at AI Infra Summit
A full system architecture breakdown of HBM, including DRAM principle of operation, DRAM/logic processes, base/core die features, and where SK Hynix/Samsung/Micron differentiate x.com/i/article/2099…
@iamfabian @TomorrowXSummit Yeah perhaps I could arrange something as a local...rooftop bar, BBQ, live music...?
Just received my TomorrowX scholarship! Heading to TomorrowX Summit 2026 in Austin, Nov 17-18. Two days with the CEOs, investors, and operators moving TMT. @TomorrowXSummit #tomorrowXsummit2026
An all-in-one co-packaged optics overview for 224Gbps+ scale-up This post is the first full-stack synthesis that effectively ties together the optical device physics, packaging, material science, and circuit design of CPO into a comprehensive high-level mental framework. siliconcodesign.com/p/co-packaged-…
"Silicon Co-Design" went from 1k to 10k followers on X in a day and #6 rising in technology on Substack! I cover the technical foundations of the underlying subsystems of AI Infra from the bottom-up, including advanced packaging, high speed optical communications, mixed-signal, power, and memory. Up until this point, I self-funded this self-education journey by travelling to flagship technical conferences (ISSCC, DesignCon, APEC, ECTC, DAC, and Hot Chips), sitting in rooms full of domain-specific experts, walking the expo floors, and learning from grad students at poster sessions. It has been a humbling journey for sure and it has not been easy to walk into these conferences without an affiliation and not feel any sense of reward. I want to thank everyone who has been with me from the beginning. Thanks @vikramskr for getting the ground running with your research and @bookwormengr on X for recently reposting my OpenAI's Jalapeno post that got me from 1k to 10k X followers.
@dnystedt Wait until physics and area density limitations come into the picture
@vikramskr @SemiAnalysis_ Sounds like Fedspeak 🫢
I run a community of around 1,000 industry professionals working in Silicon Valley and around the world. Our members work across optics, semiconductors, AI, and many other fields. @NuttyCLD, @PhotonCap, and @SVTrivo are three fantastic people I’ve met through this community. I plan to have more conversations with these experts and turn their insights into accessible articles that explain the technologies and industries they work in. Here are the expert calls currently planned: • Intel Foundry Research Engineer (Done) • Samsung HBM Packaging Engineer • ASML Research Engineer • AWS AI Research Engineer • Micron HBM Product Engineer If there are other companies you’d like to hear about, leave a comment. I’ll see what I can arrange. Thank you! Note: These interviews will focus on publicly available information and general technical knowledge. I will not discuss confidential or nonpublic company information.
Today, I had an expert call with an $INTC Foundry professional from my semiconductor industry community. It was a great opportunity to gain a deeper understanding of Intel’s technology, current position, and vision for the future. Going forward, I plan to publish more articles
A complete breakdown of the system architecture of HBM from its DDR historical foundation and alternatives for today's AI compute (GDDR7, SRAM, LPDDR6 arrays, PIM, Disaggregated Memory Pools, and HBF) x.com/i/article/2099…
The complete all-in-one system architecture breakdown of HBM. In this post I cover scaling challenges that HBM faces due to thermal, reliability, and signal integrity constraints. I ground this analysis by first covering the history of HBM and DRAM fundamentals. I also cover alternatives to HBM including HBF and other less flashy options. siliconcodesign.com/p/the-system-a…
@bookwormengr Haha thanks a lot @bookwormengr, I always wondered about how the algo works myself
Tomorrow I'll be releasing my all-in-one co-packaged optics design guide that covers all technology options and challenges in each aspect of the switch - EIC, PIC, laser, and packaging. This post will be the first of its kind that effectively bridges together the device physics, manufacturing, and circuit design of CPO for all engineers involved to better understand the big picture. Make sure you follow and subscribe to my Substack, "Silicon Co-Design" so you'll be the first one to know when it drops first thing tomorrow. (Link in comments) 👇
@altcap Yes, and first principles thinking often comes down to learning about the HW and manufacturing challenges that fundamentally limit compute scaling
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Fabricated Knowledge @fabknowledge
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The Tech Investor @TheTechInvest
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P Equity Research �... @pequityresearch
54K Followers 820 Following Research 📃 & News 🗞️ | Semiconductors & Tech | Sharing my knowledge & insights with the world 🌍 | Deep dives, research, discord in my substack!📍| PMs Open👇
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dylan ツ @demian_ai
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AI Infra Connect (For... @aiandsystems
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455 Followers 2K Following I wrangle photons, atoms, and electrons. Currently building something new. Prev: Umich, Caltech Ph.D.
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13K Followers 301 Following Managing Partner, BluBird Capital Engineer - xApple | xQualcomm | xIntel | Startup exits, Tennis player🎾, JohnsHopkins alumniYou might like
