Columbia SLD Group @ColumbiaSld
System-Level Design group at Columbia University led by Professor Luca Carloni (https://t.co/UbRx6NAMU2). sld.cs.columbia.edu New York, NY Joined October 2018-
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Happening tomorrow at 11 am! @guyeichler will present his paper "MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain Computer Interfaces" at ICCD'23 in Washington DC
We are thrilled to share that our work "SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs" has received the Best-Paper Award at the 17th IEEE/ACM International Symposium on Networks‑on‑Chip (NOCS'23)! Check out the paper at ieeexplore.ieee.org/document/10234…
Check out the list of accepted presentations and posters at OSCAR'23. Just a reminder: today is the last day for early registration! oscar-workshop.github.io/Program_2023.h… iscaconf.org/isca2023/atten…
Congrats @guyeichler on being awarded the Best Presentation at RAGE'23 for the paper "EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators" #RAGE23
We are thrilled to announce that the second edition of OSCAR, the new workshop dedicated to open-source hardware, will be co-located with ISCA in Orlando on Sunday, June 18. The abstract submission deadline is this Friday, May 5th oscar-workshop.github.io oscar-workshop.github.io/files/OSCAR_20…
Join us tomorrow (11 AM) at DATE in Antwerp for a tutorial on ESP! We'll be covering new features like accelerator design with Catapult HLS and dynamic partial reconfiguration of FPGAs! @DateConference
Looking forward to our tutorial this Sunday! Hope to see you in Vancouver!
Looking forward to our tutorial this Sunday! Hope to see you in Vancouver!
Check out the ESP Tutorial page and #ASPLOS2023 Registration instructions! esp.cs.columbia.edu/tutorials/aspl… whova.com/portal/registr…
Check out the ESP Tutorial page and #ASPLOS2023 Registration instructions! esp.cs.columbia.edu/tutorials/aspl… whova.com/portal/registr…
Join us in Vancouver for a tutorial on ESP at ASPLOS '23! We'll be covering new, exciting features like accelerator design with Catapult HLS, dynamic partial reconfiguration of FPGAs, and an intro to ASIC design with ESP! Early registration deadline is this Friday. @ASPLOSConf
A new GitHub Release of #ESP is now available: github.com/sld-columbia/e…. Check out the release notes for the complete list of #ESP features. @ColumbiaCompSci @CUSEAS
Earlier this month, we presented the paper "A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components" at ICCAD 2022. sld.cs.columbia.edu/pubs/dossantos… youtube.com/watch?v=7YMhKs…
Big Milestone for the OSH community: ESP is silicon-proven! Check out the first chip based on the #ESP platform. This work is a collaboration with Harvard and IBM Research, recently published at #ESSCIRC 2022. sld.cs.columbia.edu/pubs/jia_manto… epapers.org/ess2022/ESR/se… @ColumbiaCompSci
The official program of OSCAR 2022, the new workshop on open-source hardware, is out! Check it out at oscar-workshop.github.io/Program.html #OpenSourceHW #ISCA2022
Nice work by the team of Prof. Luca Carloni. By the way, the #riscv processor is @openhwgroup CVA6, one of the @pulp_platform open source cores!
Nice work by the team of Prof. Luca Carloni. By the way, the #riscv processor is @openhwgroup CVA6, one of the @pulp_platform open source cores!
** Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP #riscv lnkd.in/gkDSej5R
We will be presenting our work on “Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP” at the Sixth Workshop on Computer Architecture Research with RISC-V #CARRV in NYC on June 19th! arxiv.org/pdf/2206.01901… carrv.github.io/2022/
Luca took part to the Spring 2022 RISC-V Week in Paris with the talk "Open-Source Hardware for Heterogeneous Computing with ESP and RISC-V". For more info on our open-source heterogeneous SoC platform, check out the #ESP website: esp.cs.columbia.edu open-src-soc.org/2022-05/progra…
A new GitHub Release of #ESP is now available: github.com/sld-columbia/e…. Check out the release notes for the complete list of #ESP features. @ColumbiaCompSci @CUSEAS
Guy Eichler (@guyeichler) will present his paper “MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces” at ICCD's Novel Architectures session on Monday 10/25, 12:10–1:10 pm !
Guy Eichler (@guyeichler) will present his paper “MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces” at ICCD's Novel Architectures session on Monday 10/25, 12:10–1:10 pm !
Our paper "MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces" has been accepted at ICCD 2021 ! youtu.be/9a5gRrlgHRc
PULP Platform @pulp_platform
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Jon Masters 🏴�.. @jonmasters
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Samira Khan @samiramanabi
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Matt Guthaus @mrg@fos.. @mguthaus
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Akanksha @akanksha_c073
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Nimish Shah @nimish15shah
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WeShape @weshape_io
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PULP Platform @pulp_platform
6K Followers 1K Following A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.
Brendan Dolan-Gavitt @moyix
25K Followers 6K Following Associate Professor @ NYU Tandon. Security, RE, ML. PGP https://t.co/3WXr0RfRkv Founder of the MESS Lab: https://t.co/zGycrX3Gmn "an orc smiling into the camera" — CLIP
Natalie Enright Jerge.. @nenrightjerger
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Jan Gray @jangray
5K Followers 2K Following computing with FPGAs; ex MS dev tools architect; https://t.co/raSpGdhYZ3; https://t.co/xpX0gKABG6; https://t.co/i8BjreGEmx; co-chair RVI SIG-SOFT-CPU
Jon Masters 🏴�.. @jonmasters
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Rachit Nigam @notypes
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Onur Mutlu @_onurmutlu_
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Talia Ringer 🟣 �.. @TaliaRinger
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Samira Khan @samiramanabi
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4K Followers 2K Following たった一人で日本の天〇学研究遂行に重大な支障を来らせた罪人、博士 (物理) の皆様には申し訳ありませんでした。余計なツイートをしないように心掛けますが、私ごときが URL込み一次情報を紹介するのすら気に入らない方もいるので何かあったら察して↓ https://t.co/1K63SE3R0z
Niloofar (Fatemeh) Mi.. @niloofar_mire
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Computer Architecture.. @CompArchSA
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Nice work by the team of Prof. Luca Carloni. By the way, the #riscv processor is @openhwgroup CVA6, one of the @pulp_platform open source cores!
** Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP #riscv lnkd.in/gkDSej5R
** Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP #riscv lnkd.in/gkDSej5R
Prof Luca Carloni is looking for #PhD students! He leads the Systems-Level Design Group (@ColumbiaSld) in systems-on-chip research. Find out more about him cs.columbia.edu/~luca/. For info on our #computerscience PhD programs bit.ly/CSPhDprogram. The deadline is December 15.
Our paper "Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs" has been accepted at MICRO 2021! @MicroArchConf
Happening today at 8am PT! esp.cs.columbia.edu/tutorials/aspl…
Checkout the ASPLOS'21 tutorial on rapid FPGA-based prototyping of the SoCs. ESP: An Open-Source Research Platform for Agile SoC Design and Programming esp.cs.columbia.edu/tutorials/aspl… #ASPLOS21 #opensource #SoC #FPGA #prototyping
As members of the hls4ml team, we contributed to the brand new MLPerf Tiny Inference benchmark suite and results. You can also find more information in the paper we co-authored arxiv.org/abs/2106.07597
Introducing our @mlperf1 Tiny Inference benchmark, aimed at measuring ML performance and driving efficiency improvements to the smallest intelligent devices like wearables and thermostats. To view the results, please visit mlcommons.org/en/inference-t….
Introducing our @mlperf1 Tiny Inference benchmark, aimed at measuring ML performance and driving efficiency improvements to the smallest intelligent devices like wearables and thermostats. To view the results, please visit mlcommons.org/en/inference-t….
Congrats again to Joseph (@zuck_joseph) for being awarded the NSF fellowship! engineering.columbia.edu/news/31-columb…
Our paper "Accelerator Integration for Open-Source SoC Design" has been published in the IEEE Micro special issue on FPGA Computing! @ieeemicro ieeexplore.ieee.org/document/94063… sld.cs.columbia.edu/pubs/giri_ieee…
Designing digital systems and accelerating functions with HLS for FPGA is fun. youtube.com/channel/UCbepp… @jainabhishek123 @internetofshit @realhamed @ColumbiaSld @Kirshanthan @samiramanabi @johnregehr @IEEEorg @MattWindsor91
Here comes an interesting use of our Ariane. This is a recent paper "Secure and Resilient SoCs for Autonomous Vehicles" by Pradip Bose & Co. from The Workshop on Domain-Specific System Architecture (DOSSA-3) in conjunction with HPCA-27. Explore more: prism.sejong.ac.kr/dossa-3/dossa_…
How did we miss this? Our friends @antmicro have managed to support @lowRISC’s Ibex in Verilator/Yosys via UHDM/Surelog. Carl the Ibex & Bianca the Bear are very happy 🐻. antmicro.com/blog/2020/12/i… A small typo "Originally developed at ETH Zürich as RI5CY..." should be Zero-riscy.
The recordings of the #ESP tutorials at #ASPLOS and #ISPASS 2021 are now available on the ESP website and YouTube channel: esp.cs.columbia.edu/2021/04/28/tut…
Congrats @zuck_joseph on being awarded the #NSF Graduate Research Fellowship!
Congratulations to our students and alums who were named #NSFGRFP fellows: Philippe Chlenski (@pchlenski) Udai Nagpal Shashaank Narayanan Meghna Pancholi Clayton Sanford (@clayton_sanford) Joseph Zuckerman (@zuck_joseph) Alexander Bienstock
ASPLOS 2021 starts tomorrow with a rich program of workshops and tutorials that will continue throughout the whole week.
Join us for the ESP tutorial at ASPLOS on Monday April 12th!
Checkout the ASPLOS'21 tutorial on rapid FPGA-based prototyping of the SoCs. ESP: An Open-Source Research Platform for Agile SoC Design and Programming esp.cs.columbia.edu/tutorials/aspl… #ASPLOS21 #opensource #SoC #FPGA #prototyping
Checkout the ASPLOS'21 tutorial on rapid FPGA-based prototyping of the SoCs. ESP: An Open-Source Research Platform for Agile SoC Design and Programming esp.cs.columbia.edu/tutorials/aspl… #ASPLOS21 #opensource #SoC #FPGA #prototyping
Congrats to @ColumbiaCompSci Prof Al Aho, winner of the 2020 @TheOfficialACM Turing Award! The award honors his research on theory & algorithms underlying programming language & work educating generations of computer scientists bit.ly/3md7SOn @Columbia @ColumbiaAlumniA
Congratulations to our students and alums who were named #NSFGRFP fellows: Philippe Chlenski (@pchlenski) Udai Nagpal Shashaank Narayanan Meghna Pancholi Clayton Sanford (@clayton_sanford) Joseph Zuckerman (@zuck_joseph) Alexander Bienstock
We are delighted to see RI5CY and PULPino in service of other research projects. Here is the chip LEO-1, a rapid integration research platform by EnICS Labs Bar-Ilan, as featured in the EUROPRACTICE Activity report (p.33) 😀europractice-ic.com/wp-content/upl… eng.biu.ac.il/temanad/
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