FPGAzumSpass @AzumFpg

Developing with fun Joined July 2020

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FPGAzumSpass @AzumFpg

2 years ago

@Retro_is_COOL MiSTer doesn't allow button combos for key mappings as far as I know. That being said, you could of course create a special core build using a fixed combo with very little effort.

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@wickerwaka @RCAVictorCo Cannot give numbers for every situation as bandwidth depends on burst size and latency (in clock cycles) depends on the clock speed and read/write mode. But one example: at 125 Mhz you can read up to 872MByte/s with 16 clock cycles(128ns) average latency for the first word only

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FPGAzumSpass @AzumFpg

2 years ago

@wickerwaka @RCAVictorCo Yes, burst size, bandwidth and latency can all be tested with this core. I added the description from the old Patreon post to the readme of the cores github page, so it should be easier to understand what it does.

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FPGAzumSpass @AzumFpg

2 years ago

@nuxvomo Most will just use some existing workflow with e.g. DevKitArm and tonc libraries or other comparable solutions. I went that way, because I think investing time into a workflow that lets me work better and easier is worth it and pays off fast.

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FPGAzumSpass @AzumFpg

2 years ago

I'm currently working on a Rogue-like action game for the GBA. With roughly 10 minute runs it fits perfectly for a portable console. The first test version will be available soon. Once that is out, I really hope for your feedback and suggestions to make it a great game.

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FPGAzumSpass @AzumFpg

2 years ago

@nuxvomo I modified my GBA emulator and replaced the CPU with the code of the game. That way I can run it native under windows and debug with visual studio while still using PPU, DMA or APU emulation. After each coding day, I do a short test against HW to see it behaves the same.

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FPGAzumSpass @AzumFpg

2 years ago

@syke It might improve scaled or rotated content, but not the normal background layers where this functionality is not possible.

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FPGAzumSpass @AzumFpg

2 years ago

@Spokavriel It's a real time action game with controls like in Minish Cap or Shining Soul, so there are no random encounters.

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FPGAzumSpass @AzumFpg

2 years ago

@Shadoff_d Sounds good. I have zero experience with PCFX so I don't know how well the rendering features will map to it, but you can probably find a way. It's all written in C code.

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FPGAzumSpass @AzumFpg

2 years ago

@AndreaBogazzi @sixtyfps Yes, instead of outputting only half of the lines each frame, all that have been rendered are always shown.

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FPGAzumSpass @AzumFpg

2 years ago

@the_tuolomee Yes, full 480p, no deinterlacing required at all.

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FPGAzumSpass @AzumFpg

2 years ago

@hansfbaier @enjoy_digital Very kind, thank you. It's just that I don't have time for it currently with all the things I still have to do.

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FPGAzumSpass @AzumFpg

2 years ago

@v64jr No, HDMI only, sorry.

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FPGAzumSpass @AzumFpg

2 years ago

@AndreaBogazzi @sixtyfps The example (SW EP1 Racer) runs at variable fps around 20-50. With 480i, some frames only show half of the rendered image, with 480p we can see the whole image. So yes, in some case(>30fps) more information is shown. With <30 fps you at least never get combining artifacts.

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FPGAzumSpass @AzumFpg

2 years ago

@AndreaBogazzi Yes, give it right into our HDMI scaler without letting the normal video out touch it first.

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FPGAzumSpass @AzumFpg

2 years ago

@zezba9000 No, rendering in RDP is untouched. Only VI is modified/skipped and all pixels are copied to DDR3 for Misters internal scaler.

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FPGAzumSpass @AzumFpg

2 years ago

@jamesfmackenzie Not for CPU or GPU, the image is already rendered anyway, the N64 just has no output method for 480p usually. It will cost a little bit more DDR3 bandwidth, but we have way more than we need.

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FPGAzumSpass @AzumFpg

2 years ago

@dragonstomp As soon as the core is officially released, it will be part of it. I just leave some options out for now with the debug builds to be able to develop faster.

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FPGAzumSpass @AzumFpg

2 years ago

@DrLilo1 Soon™ ;)

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FPGAzumSpass @AzumFpg

2 years ago

@a1exh Depends on the situation. For this particular case you can look at the code: it's now shorter and easier to understand: github.com/RobertPeip/Mis…

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FPGAzumSpass @AzumFpg

2 years ago

I worked the last days on fixing some edge case FPU bug in the #MiSTerFPGA N64 core. There is an article on my patreon if you are interested in more technical details about the core development and researching such details.